/*
 * ram.v
 *
 * Copyright 2024 dh33ex <dh33ex@riseup.net>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301, USA or visit <http://www.gnu.org/licenses/>.
 *
 *
 */

module timer(
    input                i_rst,
    input                i_clk,

    output      [31:0]   o_rd
);

    reg [31:0]  timer;
    reg [$clog2(`SOC_FREQ):0] counter = 0;

    always @(posedge i_clk) begin
        if (i_rst) begin
            timer   <= 32'h00000000;
            counter <= 0;
        end else begin
            counter <= counter + 1;
            if (counter == (`SOC_FREQ - 1)) begin
                timer <= timer + 1;
                counter <= 0;
            end
        end
    end

    assign o_rd = timer;

endmodule
